Architecture Modeling Engineers BS Degree In Computer Science Team Lead Experience CC   Requirement id 111331 Job title Engineer Job location in Irvine, CA Skills required Architecture, Modeling, Engineers, BS Degree In Computer Science Team Lead Open Date 03-Nov-2020 Close Date Job type Direct Hire Duration 6 Months Compensation DOE Status requirement --- Job interview type Phone Screening    Email Recruiter: coolsoft Job Description Engineer: Architecture, Modeling, Engineers, BS Degree In Computer Science Team Lead Note: * LOCAL CANDIDATES ONLY * Candidates must be local to California, must relocate to Irvine, CA if needed as job is 100% onsite. Base salary is listed plus 20% annual performance bonus. Requirements Years of work experience: 5 year(s) Responsibilities POSITION DESCRIPTION SUMMARY Client is looking for an exceptional Architecture Modeling Engineer to model a complex digital SoC project. This Engineer will work in a team-oriented environment to understand the architectural specification, generate the architectural model from scratch using state-of-the-art methodologies and tools, and then validate the architecture by running test stimulus through the model. This candidate will be expected to lead a small team to accomplish the goals in a timely manner. LOCAL CANDIDATES ONLY. RESPONSIBILITIES • Develop from scratch a full-scale performance model of an SoC to validate final architecture design, throughput, latency, buffering/scheduling tradeoffs, etc. The model(s) can be transaction accurate, cycle accurate, etc. • Work closely with Architects to assess/evaluate various features and respective architectural choices, model them using high-level languages (C/C++/Python/any other/etc.), generate a complete trade-off analysis and publish results to the team. • Verify the performance model correlates with the RTL, which may involve writing verification plans, writing directed tests, and writing checkers • Lead a small team (one to two engineers) to complete the tasks in a timely manner QUALIFICATIONS AND EDUCATION • BSEE/BSCS/BSCE degree and 7-10 years of related experience, an MSEE/MSCS/MSCE degree and 5-8 years of related experience • Experience leading small teams (2-5 members) • Experience with performance modeling for full system data flow • Prior knowledge of SystemC and TLM2 • Grasp of the fundamentals of interconnects, traffic QoS, coherency flows, caches and memory controller • Proficient in C/C++ and/or Python. • Familiarity with ASIC, computer and embedded system architecture • Excellent written and verbal communication, excellent organization skills, and highly self-motivated. • Strong working knowledge of modeling tools and techniques. • Ability to summarize performance data and communicate issues effectively PREFERRED EXPERIENCE • Experience with storage/memory architectures: DDRx, HBM, NVMe, PCIe, and NAND control. • Experience with EDA modeling tools like Platform Architect, Cycle Model Studio, Matlab/Simulink. • Advanced methodology like systemVerilog-OVM or systemVerilog-UVM • Statistical analysis • Scripting (especially Python) Languages Must have English Native or bilingual proficiency Experience required • Ability to develop from scratch a full-scale performance model of an SoC to validate final architecture design, throughput, latency, buffering/scheduling tradeoffs, etc. • Experience leading small teams (2-5 members) • Experience with performance modeling for full system data flow • Prior knowledge of SystemC and TLM2 • Grasp of the fundamentals of interconnects, traffic QoS, coherency flows, caches and memory controller • Proficient in C/C++ and/or Python. • Familiarity with ASIC, computer and embedded system architecture Additional job information Candidates must be local to California, must relocate to Irvine, CA if needed as job is 100% onsite. Base salary is listed plus 20% annual performance bonus.   Call 502-379-4456 Ext 100 for more details. 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