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System Verilog OVMUVM DV Experience Digital ASICs Design Flows. Bachelors degree i
 
Requirement id 104683
Job title Engineer
Job location in Phoenix, AZ
Skills required RTL Engineer, RTL Lead Engineer, RTL Senior Enginee, System Verilog OVMUVM DV Experience Digi
Open Date 11-Mar-2020
Close Date
Job type Contract
Duration 12 Months
Compensation DOE
Status requirement ---
Job interview type ---
   Email Recruiter: coolsoft
Job Description Engineer: RTL Engineer, RTL Lead Engineer, RTL Senior Enginee, System Verilog OVMUVM DV Experience Digi

Description:

These positions are onsite M-F. No remote.

We need candidates with the following skill levels for the RTL roles:

RTL Lead Engineer (7+ yrs)
RTL Senior Engineer (4-7 yrs)
RTL Engineer (1-3 yrs)

The RTL Engineers will work with researchers and architects doing RTL design using tools such as Verilog, MatLab.

Primary Skills:

Design from conception to production.
2+ years of System Verilog OVM/UVM DV experience.
Knowledge of RTL.
Knowledge of digital ASICs design flows.
Bachelors degree in Electrical
Engineering or Computer Science or equivalent experience.

Nice to haves: ASIC verification background
 
Call 502-379-4456 Ext 100 for more details. Please provide Requirement id: 104683 while calling.
 
Other jobs in AZ: Chandler (14), Phoenix (9), Scottsdale (1), Tempe (4),
 
 
 
 
(Engineer: RTL Engineer, RTL Lead Engineer, RTL Senior Enginee, System Verilog OVMUVM DV Experience Digi in Phoenix, AZ)
   
 
     
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